Semiconductor wafer manufacturing utilizes very sophisticated wafer processing procedures and complicated manufacturing systems. In efforts to reduce the size of the semiconductor package, manufacturers have reduced component sizes including the thickness of the wafer, itself. For example, wafer thinning can be performed by a grinding method to achieve a wafer thickness on the order of 100 microns and less. These thin wafers, though, are very fragile and brittle. Of particular concern is chipping at the edges of the thinned wafers during processing (e.g., grinding).
More specifically, backside wafer thinning is required for integrated circuits for a number of reasons: smaller form factor for mobile devices, 3D stacking, and ground through silicon vias (TSVs) for power amplifiers. However, edge chipping is commonly observed during backside thinning, because the thinned wafer is especially thin at the edges due to a curvature of the bevel region.
For example, in order to perform wafer thinning, the wafer is bonded to a planar substrate. These substrates are typically planar glass or silicon substrates; whereas, the wafers have a curvature at the edges. The edges of the wafers are thus not supported during the grinding process. Once bonded to the substrate, the wafer undergoes a grinding process using conventional processes. However, the edges of wafer can crack during the grinding process due to a number of factors, including but not limited to: (i) forces applied at the edge of the wafer and (ii) the edges of the wafer being unsupported during the thinning process. That is, as the curved edges have no mechanical support, they have a tendency to crack or chip during the grinding process. A number of processes have been proposed to minimize edge chipping, including “adhesive fillet” and edge trimming; however, these processes require extra processing, which increases cost.